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Digital System Design with VHDL

Digital System Design with VHDL
By Mark Zwolinski

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Product Description

Digital Design with VHDL is intended both for students on preliminary courses in Digital Design and practitioners who would like to integrate digital design with VHDL synthesis in the workplace.  Its unique approch compbines the principles of digital design with a guide to the use of VHDL.  Synthesis issues are discussed and practical guidelines are provided for improving simulation accuracy and performance.  The reader is assumed to have some rudimentary knowledge of Boolean algebra and logic gates although the text recaps these basics in an introductory chapter.


Product Details

  • Amazon Sales Rank: #805004 in Books
  • Published on: 2000-04-03
  • Original language: English
  • Number of items: 1
  • Binding: Paperback
  • 416 pages

Editorial Reviews

From the Back Cover
Digital System Design with VHDL
Mark Zwolinski
Electronic systems based on digital principles are becoming ubiquitous. A good design approach to these systems is essential and a top-down methodology is favoured. Such an approach is vastly simplified by the use of computer modelling to describe the systems. VHDL is a design language which allows a designer to model the behaviour and structure of a digital circuit on a computer before implementation and to automatically synthesize the structure from a high-level description.
Digital System Design with VHDL is intended both for students on Digital Design courses and practitioners who would like to integrate digital design and VHDL synthesis in the workplace.
Its unique approach combines the principles of digital design with a guide to the use of VHDL. Synthesis issues are discussed and practical guidelines are provided for improving simulation accuracy and performance.
Features-
· a practical perspective is obtained by the inclusion of numerous examples
· applies software engineering practices to encourage clear coding and adequate documentation of the process
· demonstrates the effects of particular coding styles on synthesis and simulation efficiency
· covers the major VHDL standards
· includes an appendix with examples in Verilog
About the author-
Dr Mark Zwolinski is a Senior Lecturer in the Department of Electronics and Computer Science at the University of Southampton. He has written or co-authored around 50 journal and conference papers in the field of Electronic Design Automation. He is also a director of LME Ltd., who supply behavioural synthesis tools for digital system design.